From 3b633bbf1dfcd9107b8a1cc86ce8c34f6fc06fdb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 28 Apr 2017 22:36:17 +0200 Subject: cpu/intel/pineview: Include speedstep Needed to generate cpu entries. Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19496 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/socket_FCBGA559/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 082c47261b..dbf300b0d2 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c -- cgit v1.2.3