From 246ae2129eb091da06cf6275bd503dd5730060dc Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 8 Sep 2005 17:17:25 +0000 Subject: simplify code git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/emulation/qemu-i386/Config.lb | 2 + src/cpu/emulation/qemu-i386/chip.h | 6 ++ src/cpu/emulation/qemu-i386/northbridge.c | 134 ++++++++++++++++++++++++++++++ src/cpu/emulation/qemu-i386/northbridge.h | 5 ++ 4 files changed, 147 insertions(+) create mode 100644 src/cpu/emulation/qemu-i386/Config.lb create mode 100644 src/cpu/emulation/qemu-i386/chip.h create mode 100644 src/cpu/emulation/qemu-i386/northbridge.c create mode 100644 src/cpu/emulation/qemu-i386/northbridge.h (limited to 'src/cpu') diff --git a/src/cpu/emulation/qemu-i386/Config.lb b/src/cpu/emulation/qemu-i386/Config.lb new file mode 100644 index 0000000000..4a0c2c8658 --- /dev/null +++ b/src/cpu/emulation/qemu-i386/Config.lb @@ -0,0 +1,2 @@ +config chip.h +object northbridge.o diff --git a/src/cpu/emulation/qemu-i386/chip.h b/src/cpu/emulation/qemu-i386/chip.h new file mode 100644 index 0000000000..6ade17bb01 --- /dev/null +++ b/src/cpu/emulation/qemu-i386/chip.h @@ -0,0 +1,6 @@ +struct cpu_emulation_qemu_i386_config +{ +}; + +extern struct chip_operations cpu_emulation_qemu_i386_ops; + diff --git a/src/cpu/emulation/qemu-i386/northbridge.c b/src/cpu/emulation/qemu-i386/northbridge.c new file mode 100644 index 0000000000..2f1f48f995 --- /dev/null +++ b/src/cpu/emulation/qemu-i386/northbridge.c @@ -0,0 +1,134 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "northbridge.h" + +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + uint32_t idx; + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev->link[0].children; + if (mc_dev) { + unsigned long tomk, tolmk; + /* Hard code the Top of memory for now */ + tomk = 65536; + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap memory. + */ + tolmk = tomk; + } + + /* Report the memory regions */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); + if (tomk > 4*1024*1024) { + ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); + } + } + assign_resources(&dev->link[0]); +} + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } +} + +struct chip_operations cpu_emulation_qemu_i386_ops = { + CHIP_NAME("QEMU Northbridge") + .enable_dev = enable_dev, +}; + +void udelay(int usecs) +{ + int i; + for(i = 0; i < usecs; i++) + outb(i&0xff, 0x80); +} + + diff --git a/src/cpu/emulation/qemu-i386/northbridge.h b/src/cpu/emulation/qemu-i386/northbridge.h new file mode 100644 index 0000000000..c74e63b97d --- /dev/null +++ b/src/cpu/emulation/qemu-i386/northbridge.h @@ -0,0 +1,5 @@ +#ifndef NORTHBRIDGE_EMULATION_QEMU_I386_H +#define NORTHBRIDGE_EMULATION_QEMU_I386_H + + +#endif /* NORTHBRIDGE_EMULATION_QEMU_I386 */ -- cgit v1.2.3