From 242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 23 Nov 2017 21:23:44 +0100 Subject: intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/intel/model_6ex/model_6ex_init.c | 2 +- src/cpu/intel/model_6fx/model_6fx_init.c | 2 +- src/cpu/intel/speedstep/speedstep.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6e5b339444..96830c495d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -86,7 +86,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); // set maximum CPU speed - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); int busratio_max = (msr.hi >> (40-32)) & 0x1f; msr = rdmsr(IA32_PLATFORM_ID); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index b5a68ccadf..a1433f6de1 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -94,7 +94,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); // set maximum CPU speed - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); int busratio_max = (msr.hi >> (40-32)) & 0x1f; msr = rdmsr(IA32_PLATFORM_ID); diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 96ac8e59e0..441f2a36af 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -55,15 +55,15 @@ static void speedstep_get_limits(sst_params_t *const params) /* Read normal maximum parameters. */ /* Newer CPUs provide the normal maximum settings in - IA32_PLATFORM_ID. The values in IA32_PERF_STS change + IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change when using turbo mode. */ msr = rdmsr(IA32_PLATFORM_ID); params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); if (cpu_id == 0x006e) { /* Looks like Yonah CPUs don't have the frequency ratio in - IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading should be reliable as those CPUs don't have turbo mode. */ - msr = rdmsr(IA32_PERF_STS); + msr = rdmsr(IA32_PERF_STATUS); params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) >> SPEEDSTEP_RATIO_SHIFT; } -- cgit v1.2.3