From 1da104647dc2828a6594bdc7b5ae119923dbcffa Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 28 Oct 2011 20:28:03 +0200 Subject: Get rid of AUTO_XIP_ROM_BASE That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/car/cache_as_ram.inc | 14 ++++---------- src/cpu/intel/car/cache_as_ram.inc | 12 +++--------- src/cpu/intel/model_106cx/cache_as_ram.inc | 11 +++-------- src/cpu/intel/model_6ex/cache_as_ram.inc | 11 +++-------- src/cpu/intel/model_6fx/cache_as_ram.inc | 11 +++-------- src/cpu/via/car/cache_as_ram.inc | 26 +++++++++++++++----------- src/cpu/x86/mtrr/earlymtrr.c | 7 ++++++- 7 files changed, 37 insertions(+), 55 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 48992969f0..9d2b400f49 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -281,24 +281,18 @@ clear_fixed_var_mtrr_out: #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif - /* Enable write base caching so we can do execute in place (XIP) * on the flash ROM. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRPROT, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 2310d7d9d2..4ad2fce071 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -231,12 +231,6 @@ clear_fixed_var_mtrr_out: #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif - /* * Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index da14db22ae..b45599ac1b 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -102,17 +102,12 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 02de5ab50f..fa35fc9994 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -102,17 +102,12 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2f13d355fd..a8690112c8 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -109,17 +109,12 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 20b3220f87..d0c43c96c0 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -110,12 +110,6 @@ clear_fixed_var_mtrr_out: movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr -#if CONFIG_TINY_BOOTBLOCK -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif - /* * Enable write base caching so we can do execute in place (XIP) * on the flash ROM. @@ -123,11 +117,11 @@ clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* - * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $REAL_XIP_ROM_BASE, %eax + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr @@ -168,7 +162,12 @@ clear_fixed_var_mtrr_out: rep stosl #ifdef CARTEST - movl REAL_XIP_ROM_BASE, %esi + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl copy_and_run, %esi + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei movl %esi, %edi movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx rep lodsl @@ -244,7 +243,12 @@ testok: /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index dcfcccd0f3..f8119d3e59 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -29,6 +29,8 @@ static void cache_lbmem(int type) enable_cache(); } +const int addr_det = 0; + /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ @@ -52,8 +54,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) #if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. + * Determine address by calculating the XIP_ROM_SIZE sized area with + * XIP_ROM_SIZE alignment that contains the global variable defined above; */ - set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); + set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs -- cgit v1.2.3