From 168ef399c43ad79a40a8bbb2de921a2bd906b3f5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 27 Jun 2017 22:54:42 +0200 Subject: cpu/*: Add whitespace around '<<' Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/agesa/cache_as_ram.inc | 2 +- src/cpu/amd/agesa/cache_as_ram_legacy.inc | 2 +- src/cpu/amd/dualcore/amd_sibling.c | 4 ++-- src/cpu/amd/dualcore/dualcore.c | 4 ++-- src/cpu/amd/dualcore/dualcore_id.c | 4 ++-- src/cpu/amd/geode_gx2/cpubug.c | 6 +++--- src/cpu/amd/mtrr/amd_mtrr.c | 6 +++--- src/cpu/amd/pi/cache_as_ram.inc | 2 +- src/cpu/amd/quadcore/amd_sibling.c | 2 +- src/cpu/intel/car/cache_as_ram_ht.inc | 4 ++-- src/cpu/intel/haswell/smmrelocate.c | 4 ++-- src/cpu/intel/smm/gen1/smmrelocate.c | 2 +- src/cpu/via/c7/c7_init.c | 2 +- src/cpu/via/nano/nano_init.c | 12 ++++++------ 14 files changed, 28 insertions(+), 28 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 857873a682..8038177c7c 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -40,7 +40,7 @@ cache_as_ram_setup: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 post_code(0xa1) diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc index c0a69ec74a..55480070c9 100644 --- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc +++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc @@ -43,7 +43,7 @@ cache_as_ram_setup: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 /* Get the cpu_init_detected */ diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 1c003c8319..693ceb87cd 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -59,7 +59,7 @@ static void enable_apic_ext_id(int nodes) uint32_t val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } @@ -84,7 +84,7 @@ unsigned get_apicid_base(unsigned ioapic_num) if (bsp_apic_id > 0) { // IOAPIC could start from 0 return 0; - } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 + } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0 return 1; } diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 83302ca9fe..1f25668c54 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -48,11 +48,11 @@ static inline void real_start_other_core(unsigned nodeid) uint32_t dword; // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); - dword |= 1<<27; // NbMcaToMstCpuEn bit + dword |= 1 << 27; // NbMcaToMstCpuEn bit pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword); // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68); - dword |= 1<<5; + dword |= 1 << 5; pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword); } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 80ce1c7c73..e7af552dcb 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -43,14 +43,14 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<> 24) & 0xf; id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1< (uint64_t)1<<32) { + if (bsp_topmem2() > (uint64_t)1 << 32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if (has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index c0a69ec74a..55480070c9 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -43,7 +43,7 @@ cache_as_ram_setup: /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 /* Get the cpu_init_detected */ diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index c4eb50cd2c..a04ec558c0 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -64,7 +64,7 @@ static void enable_apic_ext_id(u32 nodes) u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index db779fae7e..e716caf186 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -82,7 +82,7 @@ clear_mtrrs: addrsize_no_MSR: movl $1, %eax cpuid - andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ + andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ jz addrsize_set_high movl $0x0f, %edx @@ -208,7 +208,7 @@ ap_init: /* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(1<<12), %eax + movl $(1 << 12), %eax xorl %edx, %edx wrmsr diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5c88dfa109..8d9a4dcc67 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -42,8 +42,8 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1 << 11) +#define EMRR_SUPPORTED (1 << 12) struct smm_relocation_params { u32 smram_base; diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 1da7a4ba5d..387fb8ba25 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,7 +28,7 @@ #include #include "smi.h" -#define SMRR_SUPPORTED (1<<11) +#define SMRR_SUPPORTED (1 << 11) #define D_OPEN (1 << 6) #define D_CLS (1 << 5) diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 8ddc931bea..480f61ad44 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -190,7 +190,7 @@ static void c7_init(struct device *dev) /* Enable APIC */ msr = rdmsr(0x1107); - msr.lo |= 1<<24; + msr.lo |= 1 << 24; wrmsr(0x1107, msr); /* Turn on cache */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 3a6c1a0b02..7d6338e6ee 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -104,12 +104,12 @@ static void nano_power(void) * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1<<7) | (1<<4) ); + msr.lo |= ( (1 << 7) | (1 << 4) ); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ - msr.lo |= (1<<5); + msr.lo |= (1 << 5); wrmsr(NANO_MYSTERIOUS_MSR, msr); /* Set the maximum frequency and voltage */ @@ -117,7 +117,7 @@ static void nano_power(void) /* Enable TM3 */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<3) | (1<<13) ); + msr.lo |= ( (1 << 3) | (1 << 13) ); wrmsr(MSR_IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; @@ -125,14 +125,14 @@ static void nano_power(void) /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ - msr.hi |= (1<<0); /* C4e */ + msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.hi |= (1 << 0); /* C4e */ wrmsr(MSR_IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= (1<<20); + msr.lo |= (1 << 20); wrmsr(MSR_IA32_MISC_ENABLE, msr); } -- cgit v1.2.3