From 107f72e674a3fbe2cadb24d98bba53f432bc2e0c Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 6 Jan 2014 11:06:26 +0200 Subject: Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko --- src/cpu/intel/car/cache_as_ram_ht.inc | 4 ++-- src/cpu/intel/fsp_model_206ax/cache_as_ram.inc | 4 ++-- src/cpu/intel/haswell/romstage.c | 4 ++-- src/cpu/intel/model_2065x/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_206ax/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/cpu/x86/mtrr/mtrr.c | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fe1e29a5b3..fb653168b2 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -392,7 +392,7 @@ no_msr_11e: movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax @@ -400,7 +400,7 @@ no_msr_11e: wrmsr movl $MTRRphysMask_MSR(1), %ecx rdmsr - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc index a8d7cc54cb..61fb1c2636 100644 --- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc @@ -173,7 +173,7 @@ _clear_mtrrs_: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ @@ -182,7 +182,7 @@ _clear_mtrrs_: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 35b51c5b59..edb2e80cdd 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void) /* Cache the ROM as WP just below 4GiB. */ slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid); slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); num_mtrrs++; /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index dce0e39dba..b791881d69 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -238,7 +238,7 @@ before_romstage: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ @@ -247,7 +247,7 @@ before_romstage: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index b4119cc0b9..887d92bbe6 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -250,7 +250,7 @@ before_romstage: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ @@ -259,7 +259,7 @@ before_romstage: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index ac3c66b734..baf4ae8617 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -186,14 +186,14 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d168978b54..dd404a887f 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -190,8 +190,8 @@ static struct memranges *get_physical_address_space(void) * when CONFIG_CACHE_ROM is enabled. The ROM is assumed * to be located at 4GiB - rom size. */ resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, + RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); + memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); #endif -- cgit v1.2.3