From 07921540dda79d810d8bfc6be211513c238a0d63 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 17 Jun 2016 17:22:00 +0300 Subject: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/intel/car/cache_as_ram.inc | 10 ++++++++-- src/cpu/intel/slot_1/Makefile.inc | 1 + src/cpu/intel/socket_FC_PGA370/Makefile.inc | 1 + src/cpu/intel/socket_PGA370/Makefile.inc | 1 + src/cpu/intel/socket_mFCBGA479/Makefile.inc | 1 + src/cpu/intel/socket_mPGA479M/Makefile.inc | 1 + 6 files changed, 13 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index e28d033837..349ec05f03 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -318,7 +318,12 @@ lout: /* We need to set EBP? No need. */ movl %esp, %ebp pushl %eax /* BIST */ - call main + call romstage_main + + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ + movl %eax, %ebx /* We don't need CAR from now on. */ @@ -356,7 +361,8 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $CONFIG_RAMTOP, %esp + /* Setup stack as indicated by return value from romstage_main(). */ + movl %ebx, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 992000bcfd..512571d318 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -29,3 +29,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc index fb9accc3fa..cc6e299551 100644 --- a/src/cpu/intel/socket_FC_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc @@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc index 2aed7de24c..d0f54051d6 100644 --- a/src/cpu/intel/socket_PGA370/Makefile.inc +++ b/src/cpu/intel/socket_PGA370/Makefile.inc @@ -23,3 +23,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc index e247c0966d..c84659807a 100644 --- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc +++ b/src/cpu/intel/socket_mFCBGA479/Makefile.inc @@ -7,3 +7,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc index abade4e87e..2a3187a8c0 100644 --- a/src/cpu/intel/socket_mPGA479M/Makefile.inc +++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc @@ -10,3 +10,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc +romstage-y += ../car/romstage.c -- cgit v1.2.3