From ebf142a12ce4911b766bd618483434519efba0d5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 29 Mar 2013 16:23:23 -0500 Subject: boot: add disable_cache_rom() function On certain architectures such as x86 the bootstrap processor does most of the work. When CACHE_ROM is employed it's appropriate to ensure that the caching enablement of the ROM is disabled so that the caching settings are symmetric before booting the payload or OS. Tested this on an x86 machine that turned on ROM caching. Linux did not complain about asymmetric MTRR settings nor did the ROM show up as cached in the MTRR settings. Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/x86/mtrr/mtrr.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/x86') diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 253a7c318b..608912754c 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -406,6 +407,11 @@ void x86_mtrr_disable_rom_caching(void) wrmsr(MTRRphysBase_MSR(index), msr_val); enable_cache(); } + +void disable_cache_rom(void) +{ + x86_mtrr_disable_rom_caching(); +} #endif struct var_mtrr_state { -- cgit v1.2.3