From eaab6305beb587777248bf46a894050ed2a76b78 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Fri, 21 Nov 2014 03:31:02 +1100 Subject: cpu/amd/agesa/family15rl: Provide Richland CPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Richland - Microarchitecture: Piledriver Core stepping: RL-A1 CPUID: 610F31 Change-Id: I790085fbf36d836c903dcce77d794abb8578712b Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/7537 Reviewed-by: Nicolas Reinecke Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/x86/smm/smmhandler.S | 2 +- src/cpu/x86/smm/smmrelocate.S | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/x86') diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 484b643017..5d3aae3701 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -108,7 +108,7 @@ smm_handler_start: /* This is an ugly hack, and we should find a way to read the CPU index * without relying on the LAPIC ID. */ -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) /* LAPIC IDs start from 0x10; map that to the proper core index */ subl $0x10, %ecx #endif diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 6648215e22..21c638ee35 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -24,7 +24,8 @@ /* On AMD's platforms we can set SMBASE by writing an MSR */ #if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \ - && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN + && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN \ + && !CONFIG_CPU_AMD_AGESA_FAMILY15_RL // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? -- cgit v1.2.3