From a4677e426a78f81e2a53b374f3508f717b8b2f05 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 10 Jun 2017 08:58:00 +0200 Subject: cpu/x86/smm/smihandler: Apply cosmetic changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use define for SSA base address. Move EM64T area to 0x7c00 and add reserved area of size 0x100, as there's no indication that the address 0x7d00 exists on any platform. No functional change. Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/20146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paul Menzel --- src/cpu/x86/smm/smihandler.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/cpu/x86') diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 19e53e677c..16415baac1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -153,12 +153,14 @@ void smi_handler(u32 smm_revision) case 0x00030007: state_save.type = LEGACY; state_save.legacy_state_save = - smm_save_state(smm_base, 0x7e00, node); + smm_save_state(smm_base, + SMM_LEGACY_ARCH_OFFSET, node); break; case 0x00030100: state_save.type = EM64T; state_save.em64t_state_save = - smm_save_state(smm_base, 0x7d00, node); + smm_save_state(smm_base, + SMM_EM64T_ARCH_OFFSET, node); break; case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ state_save.type = EM64T101; @@ -169,7 +171,8 @@ void smi_handler(u32 smm_revision) case 0x00030064: state_save.type = AMD64; state_save.amd64_state_save = - smm_save_state(smm_base, 0x7e00, node); + smm_save_state(smm_base, + SMM_AMD64_ARCH_OFFSET, node); break; default: printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); -- cgit v1.2.3