From 5fa5da1083d064e533b570e67370a7a477f02965 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 15 Mar 2016 09:08:34 -0500 Subject: cpu/x86/mtrr: remove early_mtrr_* functions I see no user of any of this code. Remove it. Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/14098 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov Reviewed-by: Furquan Shaikh --- src/cpu/x86/mtrr/earlymtrr.c | 77 -------------------------------------------- 1 file changed, 77 deletions(-) (limited to 'src/cpu/x86') diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 3d7ad11720..a84ecf8f72 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -18,80 +18,3 @@ void set_var_mtrr( maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } - -#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) -const int addr_det = 0; - -/* the fixed and variable MTRRs are power-up with random values, - * clear them to MTRR_TYPE_UNCACHEABLE for safety. - */ -static void do_early_mtrr_init(const unsigned long *mtrr_msrs) -{ - /* Precondition: - * The cache is not enabled in cr0 nor in MTRR_DEF_TYPE_MSR - * entry32.inc ensures the cache is not enabled in cr0 - */ - msr_t msr; - const unsigned long *msr_addr; - - /* Initialize all of the relevant msrs to 0 */ - msr.lo = 0; - msr.hi = 0; - unsigned long msr_nr; - for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) { - wrmsr(msr_nr, msr); - } - -#if defined(CONFIG_XIP_ROM_SIZE) && CONFIG_XIP_ROM_SIZE - /* enable write through caching so we can do execute in place - * on the flash rom. - * Determine address by calculating the XIP_ROM_SIZE sized area with - * XIP_ROM_SIZE alignment that contains the global variable defined above; - */ - unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); - set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); -#endif - - /* Set the default memory type and enable fixed and variable MTRRs - */ - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); - -} - -static inline void early_mtrr_init(void) -{ - static const unsigned long mtrr_msrs[] = { - /* fixed mtrr */ - 0x250, 0x258, 0x259, - 0x268, 0x269, 0x26A, - 0x26B, 0x26C, 0x26D, - 0x26E, 0x26F, - /* var mtrr */ - 0x200, 0x201, 0x202, 0x203, - 0x204, 0x205, 0x206, 0x207, - 0x208, 0x209, 0x20A, 0x20B, - 0x20C, 0x20D, 0x20E, 0x20F, - /* NULL end of table */ - 0 - }; - disable_cache(); - do_early_mtrr_init(mtrr_msrs); - enable_cache(); -} - -static inline int early_mtrr_init_detected(void) -{ - msr_t msr; - /* See if MTRR's are enabled. - * a #RESET disables them while an #INIT - * preserves their state. This works - * on both Intel and AMD cpus, at least - * according to the documentation. - */ - msr = rdmsr(MTRR_DEF_TYPE_MSR); - return msr.lo & MTRR_DEF_TYPE_EN; -} -#endif -- cgit v1.2.3