From 0da082b62542fae0f6882a90dcff7ddcf672d96d Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Tue, 29 Oct 2013 22:20:45 -0600
Subject: Update SMM for FSP systems

Add the FSP northbridge and southbridge includes.

Change-Id: I5c7f395dc033caa8d0bf0313382769595d77f2a5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/cpu/x86/smm/smmrelocate.S | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/cpu/x86/smm/smmrelocate.S')

diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index a0a5d1884f..71f74e757f 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -37,6 +37,8 @@
 #include "../../../southbridge/intel/sch/sch.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
 #include "../../../southbridge/intel/bd82x6x/pch.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
+#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
 #include "../../../southbridge/intel/i82801ix/i82801ix.h"
 #else
@@ -52,8 +54,14 @@
 #include <northbridge/intel/nehalem/nehalem.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #else
+#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
+#include <northbridge/intel/fsp_sandybridge/northbridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
 #error "Northbridge must define TSEG_BAR."
 #endif
+#endif
+
 #include <cpu/x86/mtrr.h>
 
 #endif /* CONFIG_SMM_TSEG */
-- 
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