From c6f6be0929ccef4c551f9640300972e7bc8600ec Mon Sep 17 00:00:00 2001
From: Vladimir Serbinenko <phcoder@gmail.com>
Date: Tue, 12 Nov 2013 22:32:08 +0100
Subject: Support for nehalem northbridge

Including raminit

Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 src/cpu/x86/smm/smmhandler_tseg.S | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/cpu/x86/smm/smmhandler_tseg.S')

diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
index eb5d63ca8f..fdc50536de 100644
--- a/src/cpu/x86/smm/smmhandler_tseg.S
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -60,6 +60,9 @@
 #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
+#include <northbridge/intel/nehalem/nehalem.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL
 #include <northbridge/intel/haswell/haswell.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-- 
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