From 3967cf931b02414d4b420dcb43b4aeb5ce7d2430 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 9 Aug 2020 21:33:19 +0200 Subject: cpu/x86/smm: Add a common save state handling Currently coreboot has limited use for the SMM save state. Typically the only thing needed is to get or set a few registers and to know which CPU triggered the SMI (typically via an IO write). Abstracting away different SMM save states would allow to put some SMM functionality like the SMMSTORE entry in common places. To save place platforms can select different SMM save sate ops that should be implemented. For instance AMD platforms don't need Intel SMM save state handling. Some platforms can encounter CPUs with different save states, which the code then handles at runtime by comparing the SMM save state revision which is located at the same offset for all SMM save state types. Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/x86/smm/Makefile.inc') diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index c2f49cf94d..eb386a69e5 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -32,6 +32,8 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c -- cgit v1.2.3