From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Mon, 1 Oct 2018 08:47:51 +0200
Subject: src: Move common IA-32 MSRs to <cpu/x86/msr.h>

Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.

Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/sipi_vector.S | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'src/cpu/x86/sipi_vector.S')

diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index ba5ae3e1ae..a7e4522943 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -16,6 +16,7 @@
 
 #include <cpu/x86/cr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/msr.h>
 
 /* The SIPI vector is responsible for initializing the APs in the system. It
  * loads microcode, sets up MSRs, and enables caching before calling into
@@ -25,9 +26,6 @@
 #define CODE_SEG 0x10
 #define DATA_SEG 0x18
 
-#define IA32_UPDT_TRIG 0x79
-#define IA32_BIOS_SIGN_ID 0x8b
-
 .section ".module_parameters", "aw", @progbits
 ap_start_params:
 gdtaddr:
@@ -145,7 +143,7 @@ lock_microcode:
 
 load_microcode:
 	/* Load new microcode. */
-	mov	$IA32_UPDT_TRIG, %ecx
+	mov	$IA32_BIOS_UPDT_TRIG, %ecx
 	xor	%edx, %edx
 	mov	%edi, %eax
 	/* The microcode pointer is passed in pointing to the header. Adjust
-- 
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