From d57ace259ad89ccba0b2e72036d84ff4016b1d32 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 31 Aug 2019 10:48:37 -0600 Subject: AUTHORS: Move src/cpu copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/x86/mtrr/debug.c | 2 -- src/cpu/x86/mtrr/mtrr.c | 9 +++------ 2 files changed, 3 insertions(+), 8 deletions(-) (limited to 'src/cpu/x86/mtrr') diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index c430bc1e8f..09ffa9f977 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 98449d5542..b26e31a1d4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -1,10 +1,5 @@ /* - * mtrr.c: setting MTRR to decent values for cache initialization on P6 - * - * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel - * - * Copyright 2000 Silicon Integrated System Corporation - * Copyright 2013 Google Inc. + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +11,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * + * mtrr.c: setting MTRR to decent values for cache initialization on P6 + * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel * * Reference: Intel Architecture Software Developer's Manual, Volume 3: System * Programming -- cgit v1.2.3