From 00093a81d3f54c72215d9f402c3f88880da89a81 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 2 Nov 2011 16:12:34 -0700 Subject: Add an option to keep the ROM cached after romstage Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/x86/mtrr/mtrr.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'src/cpu/x86/mtrr') diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 46d8e2d4c7..9015ad4d97 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,9 @@ #include #include #include +#include #include +#include #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; @@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; - void enable_fixed_mtrr(void) { msr_t msr; @@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) while(var_state.reg < MTRRS) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } + +#if CONFIG_CACHE_ROM + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + if (boot_cpu() && (acpi_slp_type != 3)) { + set_var_mtrr(7, (4096-4)*1024, 4*1024, + MTRR_TYPE_WRPROT, address_bits); + } +#endif + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); enable_var_mtrr(); printk(BIOS_SPEW, "Leave %s\n", __func__); -- cgit v1.2.3