From 47be2d9f70c0112da29d560cbef13b6f2bcd5697 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 12 Oct 2019 17:32:09 +0200 Subject: cpu/x86: Add a prog_run hook to set up caching of XIP stages Some platforms lack a non-eviction mode and therefore caching the whole ROM to speed up XIP stages can be dangerous as it could result in eviction if too much of the ROM is being accessed. The solution is to only cache a region, about the size of the stage that the bootblock is about to load: verstage and/or romstage. TODO: now a limit of 256KiB is set for the total amount of cache that can be used. This should fit most use cases for the time being. Change-Id: I94d5771a57ffd74d53db3e35fe169d77d7fbb8cd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35993 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/x86/mtrr/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/x86/mtrr/Makefile.inc') diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c5d2..129d05d41b 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,8 +2,12 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +verstage-y += earlymtrr.c bootblock-y += debug.c romstage-y += debug.c postcar-y += debug.c ramstage-y += debug.c + +bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -- cgit v1.2.3