From d731a24ff1b9f148609fa5052449caaab129e260 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 7 Dec 2018 14:49:20 +0100
Subject: src/cpu/intel: Set get_ia32_fsb function common

Add get_ia32_fsb returns FSB values in MHz of intel's CPUs.
Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb.

Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30103
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/lapic/apic_timer.c | 53 ++++++------------------------------------
 1 file changed, 7 insertions(+), 46 deletions(-)

(limited to 'src/cpu/x86/lapic')

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index e6a12ce387..b3ddeac17e 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <arch/cpu.h>
 #include <arch/early_variables.h>
+#include <cpu/intel/fsb.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
@@ -44,53 +45,13 @@ static u32 g_timer_fsb CAR_GLOBAL;
 
 static int set_timer_fsb(void)
 {
-	struct cpuinfo_x86 c;
-	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
-	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
-	int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
-	msr_t msr;
-
-	get_fms(&c, cpuid_eax(1));
-	switch (c.x86) {
-	case 0x6:
-		switch (c.x86_model) {
-		case 0xe:  /* Core Solo/Duo */
-		case 0x1c: /* Atom */
-			car_set_var(g_timer_fsb,
-				core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0xf:  /* Core 2 or Xeon */
-		case 0x17: /* Enhanced Core */
-			car_set_var(g_timer_fsb,
-				core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
-		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
-		case 0x3c: /* Haswell BCLK fixed at 100MHz */
-		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
-			car_set_var(g_timer_fsb, 100);
-			return 0;
-		default:
-			car_set_var(g_timer_fsb, 200);
-			return 0;
-		}
-	case 0xf: /* Netburst */
-		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
-		switch (c.x86_model) {
-		case 0x2:
-			car_set_var(g_timer_fsb,
-				f2x_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		case 0x3:
-		case 0x4:
-		case 0x6:
-			car_set_var(g_timer_fsb,
-				core2_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		}  /* default: fallthrough */
-	default:
-		return -1;
+	int ia32_fsb = get_ia32_fsb();
+
+	if (ia32_fsb > 0) {
+		car_set_var(g_timer_fsb, ia32_fsb);
+		return 0;
 	}
+	return -1;
 }
 
 static inline u32 get_timer_fsb(void)
-- 
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