From 00093a81d3f54c72215d9f402c3f88880da89a81 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 2 Nov 2011 16:12:34 -0700 Subject: Add an option to keep the ROM cached after romstage Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/boot_cpu.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/cpu/x86/lapic') diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index af20956a9a..f3fcadc0a7 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 87418d0883..0fb9d5d35c 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,7 +1,8 @@ +#include #include #if CONFIG_SMP -static int boot_cpu(void) +int boot_cpu(void) { int bsp; msr_t msr; -- cgit v1.2.3