From fcd5ace00b333ce31b11b02a2243dfbf39307f10 Mon Sep 17 00:00:00 2001
From: Eric Biederman <ebiederm@xmission.com>
Date: Thu, 14 Oct 2004 19:29:29 +0000
Subject: - Add new cvs code to cvs

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/cpu/x86/lapic/secondary.S | 53 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 src/cpu/x86/lapic/secondary.S

(limited to 'src/cpu/x86/lapic/secondary.S')

diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
new file mode 100644
index 0000000000..786c31e532
--- /dev/null
+++ b/src/cpu/x86/lapic/secondary.S
@@ -0,0 +1,53 @@
+#include <arch/asm.h>
+#include <arch/intel.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/lapic_def.h>
+	.text
+	.globl _secondary_start
+	.balign 4096
+_secondary_start:
+	.code16
+	cli
+	xorl	%eax, %eax
+	movl	%eax, %cr3    /* Invalidate TLB*/
+
+	/* On hyper threaded cpus, invalidating the cache here is
+	 * very very bad.  Don't.
+	 */
+
+	/* setup the data segment */
+	movw	%cs, %ax
+	movw	%ax, %ds
+
+	data32	lgdt	gdtaddr  - _secondary_start
+
+	movl	%cr0, %eax
+	andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
+	movl	%eax, %cr0
+
+	ljmpl $0x10, $1f
+1:	
+	.code32
+	movw	$0x18, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+
+	/* Set the stack pointer, and flag that we are done */
+	xorl	%eax, %eax
+	movl	secondary_stack, %esp
+	movl	%eax, secondary_stack
+
+	call	secondary_cpu_init
+1:	hlt
+	jmp	1b
+
+gdtaddr:
+	.word	gdt_limit	/* the table limit */
+	.long	gdt		/* we know the offset */
+
+
+.code32
-- 
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