From e135ac5a7ea69b6edcb89345019212f5de412b1e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 20 Nov 2012 11:53:47 +0100 Subject: Remove AMD special case for LAPIC based udelay() - Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer Tested-by: Stefan Reinauer --- src/cpu/x86/lapic/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu/x86/lapic/Makefile.inc') diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index f3fcadc0a7..6663c12880 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-y += boot_cpu.c -- cgit v1.2.3