From 56776a1ab39333c791903e0a7e79e8fb51d3162d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 May 2022 11:31:10 +0200 Subject: soc/amd: Do SMM relocation via MSR AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/cpu/x86/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/cpu/x86/Kconfig') diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 8d76638ff9..bd3be78b0c 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -18,6 +18,15 @@ config PARALLEL_MP_AP_WORK Allow APs to do other work after initialization instead of going to sleep. +config X86_SMM_SKIP_RELOCATION_HANDLER + bool + default n + depends on PARALLEL_MP && HAVE_SMI_HANDLER + help + Skip SMM relocation using a relocation handler running in SMM + with a stub at 0x30000. This is useful on platforms that have + an alternative way to set SMBASE. + config LEGACY_SMP_INIT bool -- cgit v1.2.3