From f1ce6f2c2518b70eae23502593393fd40fd73806 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 12 Apr 2010 09:50:53 +0000 Subject: - move the XIP_ROM_* flags to src/cpu/x86/Kconfig exclusively - set them to span the last 64k, instead of the last 128k by default - fixes via CAR for tiny bootblock - enabled tiny bootblock for via/vt8454c Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/via/car/cache_as_ram.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/via') diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 7eb85333ac..c926ab6f91 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -139,7 +139,7 @@ clear_fixed_var_mtrr_out: xorl $0x5c5c5c5c,%eax rep stosl - movl CONFIG_XIP_ROM_BASE, %esi + movl REAL_XIP_ROM_BASE, %esi movl %esi, %edi movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx rep lodsl @@ -241,10 +241,10 @@ testok: movb $0x40,%al movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax wrmsr - /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */ + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl $0x206, %ecx xorl %edx, %edx - movl $CONFIG_XIP_ROM_BASE,%eax + movl $REAL_XIP_ROM_BASE,%eax orl $(0 | 6), %eax wrmsr -- cgit v1.2.3