From 65cc526f6f47755b4492cd9fc2134fb2dd067e90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 19 Jun 2016 20:38:41 +0300 Subject: Ignore RAMTOP for MTRRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/via/car/cache_as_ram.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/via') diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 2f61b9138a..8d02e5d2ec 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -225,7 +225,7 @@ testok: movl $(MTRR_DEF_TYPE_EN), %eax wrmsr - /* Enable caching for 0..CONFIG_RAMTOP. */ + /* Enable caching for 0..CACHE_TMP_RAMTOP. */ movl $MTRR_PHYS_BASE(0), %ecx xorl %edx, %edx movl $(0x0 | MTRR_TYPE_WRBACK), %eax @@ -233,7 +233,7 @@ testok: movl $MTRR_PHYS_MASK(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Cache XIP_ROM area to speedup coreboot code. */ -- cgit v1.2.3