From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/via/car/cache_as_ram.inc | 12 ++++++------ src/cpu/via/car/cache_as_ram_post.c | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/cpu/via') diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 3bd4046649..693bce36dd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -25,8 +25,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CacheSize DCACHE_RAM_SIZE -#define CacheBase DCACHE_RAM_BASE +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase CONFIG_DCACHE_RAM_BASE #include @@ -82,13 +82,13 @@ clear_fixed_var_mtrr_out: /* MTRRPhysBase */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax + movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax wrmsr /* MTRRPhysMask */ movl $0x203, %ecx movl $0x0000000f,%edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr @@ -119,9 +119,9 @@ clear_fixed_var_mtrr_out: xorl $0x5c5c5c5c,%eax rep stosl - movl XIP_ROM_BASE, %esi + movl CONFIG_XIP_ROM_BASE, %esi movl %esi, %edi - movl $(XIP_ROM_SIZE>>2), %ecx + movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx rep lodsl /* The key point of this CAR code is C7 cache does not turn into diff --git a/src/cpu/via/car/cache_as_ram_post.c b/src/cpu/via/car/cache_as_ram_post.c index 9058727bc6..3c5c5e486b 100644 --- a/src/cpu/via/car/cache_as_ram_post.c +++ b/src/cpu/via/car/cache_as_ram_post.c @@ -78,16 +78,16 @@ and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/ "movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t" "wrmsr\n\t" - /*jasonzhao@viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/ + /*jasonzhao@viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/ "movl $0x206, %ecx\n\t" "xorl %edx, %edx\n\t" - "movl $XIP_ROM_BASE,%eax\n\t" + "movl $CONFIG_XIP_ROM_BASE,%eax\n\t" "orl $(0 | 6), %eax\n\t" "wrmsr\n\t" "movl $0x207, %ecx\n\t" "xorl %edx, %edx\n\t" - "movl $XIP_ROM_SIZE,%eax\n\t" + "movl $CONFIG_XIP_ROM_SIZE,%eax\n\t" "decl %eax\n\t" "notl %eax\n\t" "orl $(0 | 0x800), %eax\n\t" -- cgit v1.2.3