From 003d6397c6237e618e846b655283bdb9c605c518 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 31 May 2024 17:17:00 +0200 Subject: via: Start template for VIA C7 w/ CX700 northbridge The first steps to bring C7 and CX700 support back mainline. Most is skeleton copied from the `min86' example. The romstage entry is placed in the northbridge code, as that's where we'll perform raminit. Support to read the FSB frequency is added right away, same for a reset function (using CF9 reset), as both are required for a minimal build test. A mainboard VIA EPIA-EX is also introduced for build testing, and in later stages boot testing as well. Links: DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221 Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/via/car/cache_as_ram.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/cpu/via/car/cache_as_ram.S (limited to 'src/cpu/via/car/cache_as_ram.S') diff --git a/src/cpu/via/car/cache_as_ram.S b/src/cpu/via/car/cache_as_ram.S new file mode 100644 index 0000000000..5c5066d7ea --- /dev/null +++ b/src/cpu/via/car/cache_as_ram.S @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.section .init, "ax", @progbits + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt -- cgit v1.2.3