From 391ba65a9e1150ff594c881003dfebcdd18b8aba Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 31 May 2024 18:18:48 +0200 Subject: cpu/via: Implement cache as RAM The overall procedure is taken from the original code that was removed in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the start and end was updated (expect timestamp and BIST result in `xmm*' registers), stack is aligned to 16B, and linker symbols are now used for the CAR and cached XIP ranges. Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/via/c7/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/via/c7') diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index df81b3f84e..b6a970b69f 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -14,4 +14,10 @@ if CPU_VIA_C7 config DCACHE_BSP_STACK_SIZE default 0x1000 +config DCACHE_RAM_BASE + default 0xffef0000 + +config DCACHE_RAM_SIZE + default 0x10000 + endif -- cgit v1.2.3