From cf7509cfd1c775f4ee664f7784257c73bffd1513 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 22 Jun 2013 19:43:40 -0700 Subject: exynos5420: Fix the way the rate of the input clock for i2c buses is found. The clock divider was being read from registers incorrectly which meant that the periph rate was wrong. Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c Signed-off-by: Gabe Black Reviewed-on: http://review.coreboot.org/3699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/samsung/exynos5420/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/cpu/samsung') diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index e5ab001374..8c4baf8cc7 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -196,9 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_I2C9: case PERIPH_ID_I2C10: sclk = get_pll_clk(MPLL); - sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1; - div = (readl(&clk->clk_div_top0) & 0x7) + 1; - return (sclk / sub_div) / div; + div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1; + return sclk / div; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); return -1; -- cgit v1.2.3