From 5a0fdb4565dc6baf89155268dd0f52e6885197d8 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 29 Aug 2013 13:12:56 -0700 Subject: exynos5420: minor clean-up memory related stuff This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks Tested-by: David Hendricks Reviewed-by: ron minnich (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu/samsung/exynos5420/dmc_init_ddr3.c') diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index 1d7b8a8adb..2dc03b3add 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -70,12 +70,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) /* Specify the DDR memory type as DDR3 */ val = readl(&phy0_ctrl->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); - val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); writel(val, &phy0_ctrl->phy_con0); val = readl(&phy1_ctrl->phy_con0); val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); - val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); writel(val, &phy1_ctrl->phy_con0); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ @@ -142,8 +142,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) clrbits_le32(&drex0->concontrol, DFI_INIT_START); clrbits_le32(&drex1->concontrol, DFI_INIT_START); - update_reset_dll(drex0, DDR_MODE_DDR3); - update_reset_dll(drex1, DDR_MODE_DDR3); + update_reset_dll(drex0, mem->mem_type); + update_reset_dll(drex1, mem->mem_type); /* MEMBASECONFIG0 (CS0) */ writel(mem->membaseconfig0, &tzasc0->membaseconfig0); -- cgit v1.2.3