From a40435af84c5cd2175b842ff0cbd9d1e909c2ce6 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Fri, 8 Feb 2013 13:49:10 +0800 Subject: armv7/snow: Remove unused modules in bootblock and romstage. For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/2322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/samsung/exynos5250/Makefile.inc | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'src/cpu/samsung/exynos5250') diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 13baa7ef65..0a58c0c516 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,23 +3,20 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -# Clock init is done in bootblock to support UART output for -# debugging. We may add a Kconfig option to disable clock init -# in the bootblock and try moving it entirely into romstage. -bootblock-y += clock_init.c -bootblock-y += clock.c bootblock-y += pinmux.c -bootblock-y += soc.c +# Clock is required for UART +bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c +bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c +bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += clock.c romstage-y += clock_init.c +romstage-y += pinmux.c # required by s3c24x0_i2c (s5p-common) and uart. romstage-y += exynos_cache.c -romstage-y += pinmux.c -romstage-y += power.c -romstage-y += soc.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c +romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c #ramstage-y += tzpc_init.c -- cgit v1.2.3