From 9fe20cb3814df88f181648860102a9da249a4da1 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 7 Dec 2012 17:18:43 -0800 Subject: WIP: Initial support for Samsung Exynos 5250 ARM CPU Samsung SoC files, including Exynos5 (a Cortex-A15 implementation). Since this is an SoC we'll forego the x86-style {north,south}bridge and cpu distinction. We may try to split some stuff out before the final version if prudent. Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b Signed-off-by: David Hendricks Signed-off-by: Stefan Reinauer Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/2005 Tested-by: build bot (Jenkins) --- src/cpu/samsung/exynos5250/Makefile.inc | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/cpu/samsung/exynos5250/Makefile.inc (limited to 'src/cpu/samsung/exynos5250/Makefile.inc') diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc new file mode 100644 index 0000000000..556631a25a --- /dev/null +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -0,0 +1,32 @@ +romstage-y += clock.c +romstage-y += clock_init.c +romstage-y += exynos_cache.c +romstage-y += lowlevel_init.S +romstage-y += lowlevel_init_c.c +romstage-y += pinmux.c +romstage-y += power.c +romstage-y += soc.c +romstage-y += uart.c + +#ramstage-y += clock.c +#ramstage-y += clock_init.c +#ramstage-y += power.c +#ramstage-y += uart.c +##ramstage-y += spl.c +#ramstage-y += pinmux.c +##ramstage-y += tzpc_init.c +ramstage-y += clock.c +ramstage-y += clock_init.c +ramstage-y += exynos_cache.c +ramstage-y += lowlevel_init.S +ramstage-y += lowlevel_init_c.c +ramstage-y += pinmux.c +ramstage-y += power.c +ramstage-y += soc.c +ramstage-y += uart.c + +#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c +#ramstage-$(CONFIG_SATA_AHCI) += sata.c +ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c +ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c +ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c -- cgit v1.2.3