From 8cc846897132f6d6baa49118005815aefb5f560f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 9 Feb 2013 15:56:04 +0100 Subject: Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_1067x/model_1067x_init.c | 1 - src/cpu/intel/speedstep/acpi.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e81a6a7291..c821474446 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -99,7 +99,6 @@ static void enable_vmx(void) } #define MSR_BBL_CR_CTL3 0x11e -#define MSR_FSB_FREQ 0xcd static void configure_c_states(const int quad) { diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 910055d443..dfcc82e2da 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void) */ static int get_fsb(void) { - const u32 fsbcode = rdmsr(0xcd).lo & 7; + const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; switch (fsbcode) { case 0: return 800; /* / 3 == 266 */ case 1: return 400; /* / 3 == 133 */ -- cgit v1.2.3