From 8431fcb8c8e248d777723e0a6651b9030d29cf8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 10:00:28 +0300 Subject: intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15230 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/model_2065x/Makefile.inc | 1 + src/cpu/intel/model_2065x/cache_as_ram.inc | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index a13f5df26d..cdf9fed3e2 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -20,3 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 269fbeffc7..51af5c69d2 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -170,7 +170,12 @@ clear_var_mtrrs: before_romstage: post_code(0x29) /* Call romstage.c main function. */ - call main + call romstage_main + + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. + */ + movl %eax, %ebx post_code(0x2f) @@ -272,7 +277,8 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $CONFIG_RAMTOP, %esp + /* Setup stack as indicated by return value from romstage_main(). */ + movl %ebx, %esp movl %esp, %ebp call copy_and_run -- cgit v1.2.3