From 80f963ccd5989d56caee7563778705d9bfd12275 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 12 Sep 2019 15:41:32 +0300 Subject: intel/haswell: Remove some __PRE_RAM__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index f786caf3ab..4c67ba82ab 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -130,9 +130,6 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#if !defined(__ROMCC__) // FIXME romcc should handle below constructs - -#if defined(__PRE_RAM__) struct pei_data; struct rcba_config_instruction; struct romstage_params { @@ -142,18 +139,13 @@ struct romstage_params { void (*copy_spd)(struct pei_data *); }; void romstage_common(const struct romstage_params *params); -#endif -#ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* Determine if HyperThreading is disabled. The variable is not valid until - * setup_ap_init() has been called. */ -#endif /* CPU identification */ int haswell_family_model(void); @@ -161,5 +153,3 @@ int haswell_stepping(void); int haswell_is_ult(void); #endif - -#endif -- cgit v1.2.3