From 6f2d20ec490a276a087acad0b3866c0f3ee844c4 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 6 Oct 2010 19:32:39 +0000 Subject: Convert all Intel 440BX boards to Cache-as-RAM (CAR). - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/slot_1/Kconfig | 1 + src/cpu/intel/slot_1/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3639c23bf7..d10de589e7 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -19,6 +19,7 @@ config CPU_INTEL_SLOT_1 bool + select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index e51f416dab..1b68ccdabf 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -27,3 +27,5 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc + -- cgit v1.2.3