From 6bdaaefb3077938b86a65725a7732c992a0b2328 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 27 Jun 2019 06:10:38 +0300 Subject: intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prior to commit d731a24 src/cpu/intel: Set get_ia32_fsb function common value of 200 was silently used as a default for fsp_rangeley (model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb(). After the commit, get_ia32_fsb() returns -2, eventually resulting with divide-by-zero in timer_monotonic_get(), as get_timer_fsb() returns 0. Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix, using BCLK = 100 MHz based on the comments in northbridge/intel/fsp_rangeley/udelay.c Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/cpu/intel/common/fsb.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 83220de3bc..d66e87a396 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -46,6 +46,7 @@ static int get_fsb(void) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + case 0x4d: /* Rangeley BCLK fixed at 100MHz */ ret = 100; break; } -- cgit v1.2.3