From 4e6b7907de07c9c7d4b01a6213a8e13e946398cb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 2 Oct 2018 08:44:47 +0200 Subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/cpu/intel/fsp_model_206ax/finalize.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax.h | 2 +- src/cpu/intel/fsp_model_406dx/model_406dx.h | 2 +- src/cpu/intel/haswell/finalize.c | 2 +- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 8 ++++---- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/finalize.c | 2 +- src/cpu/intel/model_206ax/finalize.c | 2 +- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- 13 files changed, 21 insertions(+), 21 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 2d5973b984..d143497e2e 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -45,7 +45,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit) void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index e65b370914..1af54df71f 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -43,7 +43,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 87daeac0ea..c40b597200 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -45,7 +45,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index ce22e629e8..b170215ed3 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -48,7 +48,7 @@ void intel_cpu_haswell_finalize_smm(void) { #if 0 /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8498c1ac75..8e59ccb066 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -58,7 +58,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 24de43ec74..bba1410304 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -486,7 +486,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable msr.lo |= (1 << 28); // C1 Auto Undemotion Enable @@ -495,7 +495,7 @@ static void configure_c_states(void) msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); msr.lo &= ~0xffff; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b757..f304b948e3 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -63,7 +63,7 @@ static void configure_c_states(const int quad) const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) @@ -79,7 +79,7 @@ static void configure_c_states(const int quad) msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; @@ -129,10 +129,10 @@ static void configure_p_states(const char stepping, const char cores) wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc845b..780575a501 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -32,14 +32,14 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to // MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 8425f6afe6..08541c0d89 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit) void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 7d3cc2ee0e..5c69ffc368 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit) void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 3cc8d823fb..ece89712b0 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -252,14 +252,14 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 28); // C1 Auto Undemotion Enable msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection msr.lo |= 7; // No package C-state limit - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); msr.lo &= ~0x7ffff; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c495d..68be5679c8 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -33,7 +33,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk @@ -43,7 +43,7 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6de1..642201cc5e 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -33,7 +33,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States @@ -44,7 +44,7 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; -- cgit v1.2.3