From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 1 Oct 2018 08:47:51 +0200 Subject: src: Move common IA-32 MSRs to Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth Reviewed-by: Lijian Zhao Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/common/common_init.c | 16 ++++++---------- src/cpu/intel/fsp_model_206ax/model_206ax.h | 13 ------------- src/cpu/intel/fsp_model_406dx/model_406dx.h | 13 ------------- src/cpu/intel/haswell/haswell.h | 13 ------------- src/cpu/intel/haswell/haswell_init.c | 7 +++---- src/cpu/intel/model_1067x/model_1067x_init.c | 6 +++--- src/cpu/intel/model_106cx/model_106cx_init.c | 1 - src/cpu/intel/model_2065x/model_2065x.h | 13 ------------- src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++-- src/cpu/intel/model_206ax/common.c | 2 -- src/cpu/intel/model_206ax/model_206ax.h | 15 --------------- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/model_6ex/model_6ex_init.c | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 1 - src/cpu/intel/smm/gen1/smmrelocate.c | 4 ---- src/cpu/intel/speedstep/speedstep.c | 2 +- src/cpu/intel/turbo/turbo.c | 10 +++++----- 17 files changed, 22 insertions(+), 103 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 8dd8559d23..02eb0e201e 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -20,10 +20,6 @@ #include #include "common.h" -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) - void set_vmx(void) { struct cpuid_result regs; @@ -105,7 +101,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) config->version = version; - msr.addrl = MSR_IA32_HWP_CAPABILITIES; + msr.addrl = IA32_HWP_CAPABILITIES; /* * Highest Performance: @@ -141,7 +137,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; - msr.addrl = MSR_IA32_HWP_REQUEST; + msr.addrl = IA32_HWP_REQUEST; /* * Desired Performance Register: @@ -182,7 +178,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) */ config->regs[CPPC_COUNTER_WRAP] = unsupported; - msr.addrl = MSR_IA32_MPERF; + msr.addrl = IA32_MPERF; /* * Reference Performance Counter Register: @@ -192,7 +188,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 0; config->regs[CPPC_REF_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_APERF; + msr.addrl = IA32_APERF; /* * Delivered Performance Counter Register: @@ -200,7 +196,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) */ config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; - msr.addrl = MSR_IA32_HWP_STATUS; + msr.addrl = IA32_HWP_STATUS; /* * Performance Limited Register: @@ -210,7 +206,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 2; config->regs[CPPC_PERF_LIMITED] = msr; - msr.addrl = MSR_IA32_PM_ENABLE; + msr.addrl = IA32_PM_ENABLE; /* * CPPC Enable Register: diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 1af54df71f..29013f2a15 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -20,25 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index c40b597200..6c5cc313b4 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -21,25 +21,12 @@ /* Rangeley bus clock is fixed at 100MHz */ #define RANGELEY_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8e59ccb066..3dfdd8d071 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -35,25 +35,12 @@ #define HASWELL_BCLK 100 #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index bba1410304..1f8d7c3fff 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -649,10 +649,10 @@ static void set_energy_perf_bias(u8 policy) return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", policy); @@ -661,11 +661,10 @@ static void set_energy_perf_bias(u8 policy) static void configure_mca(void) { msr_t msr; - const unsigned int mcg_cap_msr = 0x179; int i; int num_banks; - msr = rdmsr(mcg_cap_msr); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index f304b948e3..7eb121effd 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -190,7 +190,7 @@ static void configure_misc(const int eist, const int tm2, const int emttm) const u32 sub_cstates = cpuid_edx(5); - msr = rdmsr(IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 3); /* TM1 enable */ if (tm2) msr.lo |= (1 << 13); /* TM2 enable */ @@ -220,11 +220,11 @@ static void configure_misc(const int eist, const int tm2, const int emttm) if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) msr.hi &= ~(1 << (38 - 32)); - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); if (eist) { msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 780575a501..56598fae82 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -56,7 +56,6 @@ static void configure_c_states(void) wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f87ba77460..11d86cdf89 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,26 +20,13 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 322e814e0d..222c2ed9bd 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -231,10 +231,10 @@ static void set_energy_perf_bias(u8 policy) msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 9775efb30d..1e832c8e60 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -19,8 +19,6 @@ #include #include "model_206ax.h" -#define IA32_PLATFORM_ID 0x17 - int get_platform_id(void) { msr_t msr; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 98203b66c8..f4d469c9cf 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -20,27 +20,12 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define IA32_MC0_STATUS 0x401 -#define IA32_MCG_CAP 0x179 - #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ece89712b0..da869567b6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -401,10 +401,10 @@ static void set_energy_perf_bias(u8 policy) msr_t msr; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", policy); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 68be5679c8..5041dcd51d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -58,7 +58,6 @@ static void configure_c_states(void) wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 642201cc5e..c5659f381f 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -59,7 +59,6 @@ static void configure_c_states(void) wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 #define IA32_PECI_CTL 0x5a0 static void configure_misc(void) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5d78efd3de..7c492179fe 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -36,10 +36,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK_BIT (1 << 0) -#define SMRR_ENABLE (1 << 3) - struct ied_header { char signature[10]; u32 size; diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 441f2a36af..43d5b5a56b 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -72,7 +72,7 @@ static void speedstep_get_limits(sst_params_t *const params) msr = rdmsr(MSR_FSB_CLOCK_VCC); if ((msr.hi & (1 << (63 - 32))) && /* supported and */ - !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { /* not disabled */ params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); params->turbo.is_turbo = 1; diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 5583c46ea9..c31f4c0e3b 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -68,7 +68,7 @@ int get_turbo_state(void) cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); if (!turbo_cap && turbo_en) { @@ -97,9 +97,9 @@ void enable_turbo(void) /* Only possible if turbo is available but hidden */ if (get_turbo_state() == TURBO_DISABLED) { /* Clear Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi &= ~H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_ENABLED); @@ -115,9 +115,9 @@ void disable_turbo(void) msr_t msr; /* Set Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi |= H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_UNAVAILABLE); -- cgit v1.2.3