From 1083a4d2324ce54f0a9f77098c8d7c23839c3849 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 27 Feb 2019 14:29:24 +0100 Subject: cpu/intel: Remove models 69x and 6dx These came for the Socket 479 which is not supported anymore. Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/31644 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/Kconfig | 2 -- src/cpu/intel/model_69x/Kconfig | 8 ------ src/cpu/intel/model_69x/Makefile.inc | 3 -- src/cpu/intel/model_69x/model_69x_init.c | 48 ------------------------------- src/cpu/intel/model_6dx/Kconfig | 8 ------ src/cpu/intel/model_6dx/Makefile.inc | 3 -- src/cpu/intel/model_6dx/model_6dx_init.c | 49 -------------------------------- 7 files changed, 121 deletions(-) delete mode 100644 src/cpu/intel/model_69x/Kconfig delete mode 100644 src/cpu/intel/model_69x/Makefile.inc delete mode 100644 src/cpu/intel/model_69x/model_69x_init.c delete mode 100644 src/cpu/intel/model_6dx/Kconfig delete mode 100644 src/cpu/intel/model_6dx/Makefile.inc delete mode 100644 src/cpu/intel/model_6dx/model_6dx_init.c (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index bdf5b5469d..f88e631729 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -3,9 +3,7 @@ source src/cpu/intel/model_6xx/Kconfig source src/cpu/intel/model_65x/Kconfig source src/cpu/intel/model_67x/Kconfig source src/cpu/intel/model_68x/Kconfig -source src/cpu/intel/model_69x/Kconfig source src/cpu/intel/model_6bx/Kconfig -source src/cpu/intel/model_6dx/Kconfig source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig deleted file mode 100644 index ff1d5e2609..0000000000 --- a/src/cpu/intel/model_69x/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CPU_INTEL_MODEL_69X - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc deleted file mode 100644 index 7bf028c867..0000000000 --- a/src/cpu/intel/model_69x/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -ramstage-y += model_69x_init.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c deleted file mode 100644 index fe7d2ca4e0..0000000000 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void model_69x_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_69x_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */ - { X86_VENDOR_INTEL, 0x0695 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig deleted file mode 100644 index edbeac82de..0000000000 --- a/src/cpu/intel/model_6dx/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CPU_INTEL_MODEL_6DX - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc deleted file mode 100644 index 92985eab7c..0000000000 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -ramstage-y += model_6dx_init.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c deleted file mode 100644 index 337b6131df..0000000000 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -static void model_6dx_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_6dx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - /* Pentium M on 90nm with 2MiB of L2 cache */ - { X86_VENDOR_INTEL, 0x06D0 }, - { X86_VENDOR_INTEL, 0x06D6 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; -- cgit v1.2.3