From 66538e08770794b4bf7baadc53f167a405b870bc Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 5 May 2021 14:46:14 +0200
Subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.

This fixes building when some debug options are enabled.

Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/cpu/intel/socket_p/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/intel/socket_p')

diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig
index 4b99acead2..552ed7088c 100644
--- a/src/cpu/intel/socket_p/Kconfig
+++ b/src/cpu/intel/socket_p/Kconfig
@@ -12,7 +12,7 @@ config DCACHE_RAM_BASE
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x8000
+	default 0x10000
 
 config DCACHE_BSP_STACK_SIZE
 	hex
-- 
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