From 6a8ce0d250f4dbaa2f253e566cf76e20f753d131 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 17 May 2018 17:22:51 +0300 Subject: cpu/intel/car: Prepare for some POSTCAR_STAGE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/cpu/intel/socket_mPGA604/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/intel/socket_mPGA604') diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 98306d4fa6..717c5c2b6a 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -9,5 +9,10 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +ifneq ($(CONFIG_POSTCAR_STAGE),y) cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +else +cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +postcar-y += ../car/p4-netburst/exit_car.S +endif romstage-y += ../car/romstage.c -- cgit v1.2.3