From 7a39446ec236b9eeba7454790fc32fc4240d7e42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 13 Feb 2012 13:38:27 +0200 Subject: Intel cpus: Include CAR from socket MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was not obvious which CAR was compiled in. Also build would fail if a socket included two models with both having an include for CAR. Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/intel/socket_mFCPGA478/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu/intel/socket_mFCPGA478/Makefile.inc') diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index 74433a278a..29973af77a 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -12,3 +12,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -- cgit v1.2.3