From 773485b8920145443da8b09712553c10c954fed1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 22 Dec 2014 16:33:24 +0200 Subject: intel CAR: Fix DCACHE_RAM_BASE for old sockets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/cpu/intel/socket_mFCBGA479/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/cpu/intel/socket_mFCBGA479/Kconfig') diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig index 5576623be0..74508549e3 100644 --- a/src/cpu/intel/socket_mFCBGA479/Kconfig +++ b/src/cpu/intel/socket_mFCBGA479/Kconfig @@ -3,3 +3,15 @@ config CPU_INTEL_SOCKET_MFCBGA479 select CPU_INTEL_MODEL_6BX select MMX select SSE + +if CPU_INTEL_SOCKET_MFCBGA479 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + +endif -- cgit v1.2.3