From 3ab6157edec3a97945cae93320da809c243843b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 29 May 2021 21:54:26 +0300 Subject: cpu/intel/hyperthreading: Build only for selected models MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implements intel_sibling_init() that is mostly superseded. Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55201 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/socket_LGA775/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/cpu/intel/socket_LGA775/Makefile.inc') diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 8cc9a94ef9..9b571f5cb6 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/p4-netburst/cache_as_ram.S -- cgit v1.2.3