From 19e7273ec2dc243b4089b9aeeaf7929ff5a20a34 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 11 Jan 2019 23:56:51 +0100 Subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup. This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs. Tested on Foxconn D41S, still boots. Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/intel/socket_FCBGA559/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/socket_FCBGA559/Makefile.inc') diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7993294a17..868f6e5608 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -postcar-y += ../car/p4-netburst/exit_car.S +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c -- cgit v1.2.3