From e69461dc25193bc792ba50b7d48081bdccd6e066 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 5 May 2021 14:45:28 +0200
Subject: nb/intel/pineview: Use cbfs mcache

There is plenty of cache available to increase DCACHE_RAM_SIZE to
allow the use of cbfs mcache.

Tested on Gigabyte GA-D510UD, still boots and resumes.

Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/cpu/intel/socket_FCBGA559/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/intel/socket_FCBGA559/Kconfig')

diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 681ca41682..ed661b6e9c 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -17,7 +17,7 @@ config DCACHE_RAM_BASE
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x4000
+	default 0x8000
 
 config DCACHE_BSP_STACK_SIZE
 	hex
-- 
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