From a5b06b9b578f48b30502bba04841f06cf9ce9e4a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 13 Jan 2023 09:33:03 +0100 Subject: cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes building lenovo/x200 with VBOOT. All supported CPUs have enough L2 cache to support this. Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth Reviewed-by: Kyösti Mälkki --- src/cpu/intel/socket_BGA956/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/socket_BGA956/Kconfig') diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index b56fb88677..7c42722e82 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -10,7 +10,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x8000 + default 0x10000 config DCACHE_BSP_STACK_SIZE hex -- cgit v1.2.3