From 67031a565b3179fa5a28282fc2e24b47d16003e8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 5 Feb 2018 19:08:03 +0100 Subject: cpu/intel/sandybridge: Put stage cache into TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/smm/gen1/smmrelocate.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/intel/smm') diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index da43de09fd..e80fa31489 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -132,6 +132,10 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->ied_base = tsegmb + params->smram_size; params->ied_size = tseg_size - params->smram_size; + /* Adjust available SMM handler memory size. */ + if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; -- cgit v1.2.3