From 6f8b7df8ab69cd2be7d024dfbd7fbeb3a684c6b3 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 8 Oct 2016 18:42:46 +0200 Subject: cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An epic battle to fix Nehalem finally ended when we found an odd mask set in SMRR. This was caused by a wrong calculation of TSEG size. It was assumed that TSEG spans the whole space between TSEG base and GTT. This is wrong as TSEG base might have been aligned down. TEST: On X201, copied 1GiB from usb key to sd-card and verified. Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7 Found-by: Alexander Couzens, Nico Huber Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/16939 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexander Couzens Reviewed-by: Kyösti Mälkki --- src/cpu/intel/smm/gen1/smi.h | 2 +- src/cpu/intel/smm/gen1/smmrelocate.c | 19 +++++++------------ 2 files changed, 8 insertions(+), 13 deletions(-) (limited to 'src/cpu/intel/smm/gen1') diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 49009ab0d1..c328eae91a 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -15,6 +15,6 @@ void southbridge_smm_init(void); void southbridge_trigger_smi(void); void southbridge_clear_smi_status(void); -void northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size); +u32 northbridge_get_tseg_base(void); int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 06b140ea0e..7e7f986ccf 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -114,22 +114,17 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 tseg_size; - u32 tsegmb; - int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - northbridge_get_tseg_base_and_size(&tsegmb, &tseg_size); + const u32 tsegmb = northbridge_get_tseg_base(); + /* TSEG base is usually aligned down (to 8MiB). So we can't + derive the TSEG size from the distance to GTT but use the + configuration value instead. */ + const u32 tseg_size = CONFIG_SMM_TSEG_SIZE; + /* The SMRAM available to the handler is 4MiB + since the IEDRAM lives at TSEGMB + 4MiB. */ params->smram_base = tsegmb; params->smram_size = 4 << 20; params->ied_base = tsegmb + params->smram_size; -- cgit v1.2.3